The present invention generally relates to a high density stacked semiconductor package and a method for fabrication and more particularly, relates to a high density stacked semiconductor package that is formed on a substrate and arranged in a serpentine configuration and a method for such fabrication.
Stacked semiconductor packages have been used in recent years for achieving high density packaging on limited circuit board real-estate. A conventional stacked semiconductor package is formed by stacking semiconductor dies in an up-and-down configuration and then connecting the lead frames, or lead fingers from each die, together for electrical communication with an outside circuit. In the lead frame-type stacked semiconductor packages, the total thickness of the package achieved cannot be efficiently reduced in order to reduce the real-estate required for mounting a package. Furthermore, the dies that are packaged together are in electrical communication such that there is little flexibility in the application of the stacked packages. There has been little technology developed for forming stacked semiconductor packages for IC chips.
It is therefore an object of the present invention to provide a stacked semiconductor package that is formed of flip-chip bonded elements that does not have the drawbacks or shortcomings of the conventional stacked semiconductor packages.
It is another object of the present invention to provide a stacked semiconductor package that can be formed by flip-chip bonded elements each consisting of an IC die and an electronic substrate.
It is a further object of the present invention to provide a stacked semiconductor package that is formed on a substrate wherein the substrate can be folded onto itself.
It is another further object of the present invention to provide a stacked semiconductor package that is formed on a substrate and arranged in a serpentine configuration.
It is still another object of the present invention to provide a stacked semiconductor package that is formed on a substrate of polyimide.
It is yet another object of the present invention to provide a stacked semiconductor package that is formed on a substrate wherein IC dies are first flip-chip bonded to substrates and are then bonded to each other in a back-to-back relationship.
It is still another further object of the present invention to provide a method for forming a stacked semiconductor package on a substrate in a serpentine configuration.
In accordance with the present invention, a stacked semiconductor package formed on a substrate and arranged in a serpentine configuration and a method for fabricating such package are disclosed.
In a preferred embodiment, a stacked semiconductor package formed on a substrate arranged in a serpentine configuration is provided which includes a first substrate section that is formed on a first section of the substrate which has an insulating layer bonded to and a first plurality of I/O pads formed on a bottom surface, a first plurality of solder balls formed on the first plurality of I/O pads, a second plurality of I/O pads formed on a top surface through the first section of the substrate, a second plurality of solder bumps formed on the second plurality of I/O pads, and a third plurality of metal wiring formed in the insulating layer providing electrical communicating between the first plurality of I/O pads and the second plurality of I/O pads; a first IC die that has a fourth plurality of solder bumps formed in an active surface for bonding to the second plurality of solder bumps formed in the first substrate section; a second substrate section formed on a second section of the substrate that has an insulating layer bonded to and a first plurality of I/O pads formed on a top surface, a second plurality of I/O pads formed on a bottom surface through the second section of the substrate, a second plurality of solder bumps formed on the second plurality of I/O pads, and a third plurality of metal wiring formed in the insulating layer providing electrical communication between the first and the second plurality of I/O pads; a second IC die that has a fourth plurality of solder bumps formed in an active surface for bonding to the second plurality of solder bumps formed in the second substrate section; and a first U-shaped section of the substrate integrally connecting the first and the second section of the substrate such that an inactive surface of the first IC die is adhesively bonded to an inactive surface of the second IC die in a back-to-back relationship forming the stacked semiconductor package.
The stacked semiconductor package may further include a third substrate section having a structure substantially similar to the first substrate section; a third IC die that has a structure substantially similar to the first IC die; a fourth substrate section that has a structure substantially similar to the second substrate section; a fourth IC die that has a structure substantially similar to the second IC die; a second U-shaped section of the substrate integrally connecting the second and the third section of the substrate such that the top surface of the second substrate section is bonded to the bottom surface of the third substrate section by an electrically insulating adhesive; and a third U-shaped section of the substrate integrally connecting the third and the fourth sections of the substrate such that an inactive surface of the third IC die is adhesively bonded to an inactive surface of the fourth IC die in a back-to-back relationship forming the stacked semiconductor package. The package may further include a printed circuit board bonded to the first plurality of solder balls, or a passivation layer on the top and the bottom surfaces of the first and the second substrate sections for insulating the first and the second plurality of I/O pads.
The stacked semiconductor package may further include a metal lead layer on the top surface of the first substrate section and the bottom surface of the second substrate section for providing electrical communication between the two substrate sections. The package may further include an underfill layer for filling a gap formed between the second plurality of solder bumps and the top surface of the first substrate section and the second plurality of solder bumps on the bottom surface of the second substrate section. The underfill layer may be formed of an elastomeric material, while the passivation layer may be a solder mask. The substrate may be formed of a polymeric material, while the metal lead layer may be formed of copper. The package may further include a heat sink adhesively bonded between the first IC die and the second IC die.
The present invention is further directed to a method for forming a stacked semiconductor package on a substrate in a serpentine configuration which can be carried out by the operating steps of first providing a substrate of continuous length; laminating a plurality of insulating substrates to a bottom surface of the substrate in a spaced-apart relationship; forming a first plurality of I/O pads on a bottom surface of each of the plurality of insulating substrates insulated from each other by a passivation layer; forming a first plurality of solder balls on the first plurality of I/O pads; forming a second plurality of I/O pads in the substrate on top of each plurality of insulating substrates, each of the second plurality of I/O pads in electrical communication with one of the first plurality of I/O pads by metal wiring provided in the insulating substrate; forming a second plurality of solder bumps on the second plurality of I/O pads; providing a first IC die that has a second plurality of solder bumps formed on an active surface; bonding the second plurality of solder bumps on the substrate to the second plurality of solder bumps on the first IC die by mounting the first IC die on top of the substrate in a face-down position; dispensing an adhesive on an upward-facing inactive surface of the first IC die; and folding the substrate such that the first IC die is bonded to a second IC die in a back-to-back relationship forming the stacked semiconductor package.
The method for forming a stacked semiconductor package may further include the steps of adhesively bonding a third IC die to a fourth IC die in a back-to-back relationship, and a second insulating substrate to a third insulating substrate in a back-to-back relationship. The method may further include the step of bonding the first plurality of solder balls to a plurality of conductive pads on a printed circuit board, or the step of forming the first and second plurality of I/O pads by a photolithographic method, or the step of forming the first and second plurality of I/O pads in a conductive metal selected from the group consisting of Al, Cu, Al alloys and Cu alloys. The method may further include the step of forming the first and second plurality of solder bumps by a method selected from the group consisting of electroplating, screen printing, stencil printing and electroless plating. The method may further include the step of bonding a heat sink between the first IC die and the second IC die. The method may further include the step of dispensing the adhesive in a thermally conductive adhesive that contains metal particles, or the step of dispensing an underfill material in a gap formed between the first and the second plurality of solder bumps.